Work Overview
2023H Phase-Locking and Phase Modulation
Centered on Verilog-based phase measurement and STM32 execution-side coordination, a dual phase-locking debugging scheme is formed, with FPGA as the primary decision-maker and STM32 as the auxiliary phase modulator.
2024C Homologous Waveform Phase Shifting
Based on synchronous ADC/DAC DMA acquisition and output with phase offset, homologous waveform phase shifting is realized, incorporating FFT frequency measurement and serial screen parameter adjustment.
Laboratory Cloud Storage Service
Centered on the long-term accumulation of competition resources, a laboratory data station is built and maintained, supporting login isolation, video playback, large file upload, and external hard drive migration.
Hardware debugging of phase-locking and phase modulation for electronic design competition preparation, along with laboratory data service maintenance
This page showcases the three most representative outputs from my training in electronic design competitions: FPGA and STM32 collaborative phase-locking/phase modulation schemes, DMA real-time link and frequency measurement auxiliary system for homologous waveform phase shifting, and a self-built cloud storage service continuously maintained for the long-term accumulation of competition code, videos, and documents in the laboratory.
Project 1: 2023H FPGA + STM32 Phase Locking and Phase Adjustment
This project corresponds to the public repository NUEDC-2023H-PhaseControl-FPGASTM32The core idea is to first set the target sampling point in Verilog, then use the FPGA to measure the phase of the conditioned square wave, compare the current phase difference with the preset phase difference, and finally drive the state machine into different adjustment stages.
Digital Setting of Target Phase
The target phase is expressed by presetting sampling points in Verilog. For example, at 20kHz, the sampling point index is used to map the target angle, and the real-time measured phase difference is compared with the target value.
FPGA Phase Measurement Main Decision
The FPGA is responsible for measuring the phase of the conditioned square wave and uses a state machine to distinguish three debugging states: `IDLE`, `ADJUST`, and `WAIT`, forming a hardware-based main control decision chain.
STM32 Collaborative Execution
In the `ADJUST` state, handshaking with the STM32 is performed via `PE0 / PE1`: one line signals entry into the phase stabilization stage, and the other line indicates whether to advance or delay the phase.
Dual Phase-Locking Approach
Instead of relying on a single loop, the subtractor-based phase locking and the phase adjustment locking are combined to form a dual phase-locking debugging path of "FPGA decision + STM32 execution".
Project 2: 2024C Coherent Waveform Phase Locking and Adjustment
This project corresponds to the public repository NUEDC-HDU2024C-SameSourceSetPhaseCompared with the 2023H solution, this version places greater emphasis on the real-time performance of the coherent waveform phase-shifting link:First, a high-speed comparator is used for interrupt edge detection; then, `ADCDMA` and `DACDMA` are configured to achieve synchronized sampling and output as much as possible; finally, phase shifting is realized by adjusting the starting index of `ADCBUFF`.
Interrupt Edge Synchronous Triggering
A high-speed voltage comparator generates an edge signal square wave, and the interrupt edge is used as the alignment reference for real-time processing, ensuring that the sampling and output links are as synchronized and coherent as possible.
ADCDMA / DACDMA Direct Input/Output
The key to the real-time link is DMA direct pass-through, which reduces jitter caused by CPU intervention and achieves waveform phase offset by modifying the starting index of `ADCBUFF`.
Frequency Measurement and Oscilloscope Auxiliary Link
The repository description explicitly includes FFT-based frequency measurement and a simple oscilloscope function, sending frequency information to the DAC-side control microcontroller to avoid slowing down the stringent latency link.
Serial Screen Parameter Adjustment
The project directory contains the `USARTLCD` module, and the repository description also mentions adjusting the phase and observing frequency measurement results via the serial screen, forming a more complete human-computer interaction loop.
The effective operating range of this solution is approximately 100 Hz to 2 kHz. 10kHz , the system enters a metastable region, leading to increased phase jitter and degraded center-value accuracy.
Project Three: Laboratory Cloud Drive and Host Operation & Maintenance
Beyond solving problems, I also continuously maintain the data service used internally by the laboratory, consolidating past electronic design competition code, videos, documents, and shared materials.
User Isolation and Basic File Services
The server implements login-based isolation via Express and session, with independent directories for different users, and supports basic file operations such as browsing, downloading, directory creation, moving, and deletion.
Large File and Text Material Processing
It supports batch upload, total large file size limits, favorites, share links, and online reading/writing of Markdown / TXT files, making it suitable for consolidating problem materials, experiment instructions, and training records.
Video Playback and Transcoding Cache
For training and demo videos, the server implements Range-based video streaming, on-demand ffmpeg transcoding cache, and transcoding status queries, enhancing the online playback experience.
Storage Migration and Long-Term Operation & Maintenance
Supports automatic recognition of external hard drives, historical data migration, cache directory fallback, capacity status polling, and Nginx deployment. Designed for long-term laboratory operation rather than one-time demonstration.
For me, this part of the work reflects not a single algorithmic capability, but rather the engineering responsibility of preserving competition outcomes and enabling subsequent researchers to continue using them. Compared to merely writing code, the sustained maintenance of such services more closely resembles the real collaborative environment of a laboratory.
Public Repository Card
ChrisChan114514/NUEDC-2023H-PhaseControl-FPGASTM32
2023H: FPGA phase detection + STM32 coordinated phase-locking and phase-shifting project
ChrisChan114514/NUEDC-HDU2024C-SameSourceSetPhase
2024C: Same-source waveform phase-locking and shifting scheme based on DMA passthrough, FFT frequency measurement, and serial screen interaction